1) Field of the Invention
The present invention relates to an apparatus and a method for making fault diagnosis to detect a manufacturing failure (fault) of an integrated circuit such as an LSI (Large Scale Integration) or the like and specify a position at which the fault occurs, and an integrated circuit having a function of accomplishing the fault diagnosis.
2) Description of the Related Art
Detection of a manufacturing failure of an integrated circuit such as an LSI is done by applying an appropriate signal value to an input pin of the LSI using a tester (ATE; Automatic Test Equipment), and comparing a signal value appearing at the output pin with an expected result. The signal value applied to the input pin and the expected value to be appeared at the output pin are together called a test pattern.
Defect occurring inside an LSI due to a manufacturing failure of the LSI is called fault. To verify all faults that may occur inside the LSI, a large number of test patterns are required. A rate of the number of faults that can be verified by a certain test pattern to the number of all assumptive faults that are assumed inside an LSI is called fault coverage, used as a scale when the quality of the test pattern is measured. When the LSI includes sequential circuit elements [flip-flop (F/F), latch and RAM (Random Access Memory)], complexity of creation of test patterns is greatly increased.
In LSIs, scan design is general. In a scan-designed LSI, a shift register (called a scan path) is formed with sequential circuit elements (F/Fs, mainly) inside the LSI, a desired value is shifted into the shift register in a test, and a value of the shift register is read out after a clock has been applied.
In such circuits, widely adopted is deterministic stored pattern test (hereinafter referred as DSPT). DSPT is made by storing test patterns generated by an automatic test pattern generator (hereinafter referred as an ATPG) in a tester (an ATE).
FIG. 6 is a diagram for illustrating a known scan design. FIG. 6 shows a concept of the scan design as a block diagram. In a scan-designed LSI, there are formed a plurality of scan paths (shift registers) which are paths for testing the LSI, as shown in FIG. 6. Each of the scan paths is formed with a plurality of F/Fs, each of which is a memory element. Test patterns are shifted into the scan paths from their ends (the left side in FIG. 6), and results of the test are outputted from the other ends (the right side in FIG. 6). Incidentally, FIG. 6 shows four scan paths, and each of the scan paths is formed by serially connecting eight F/Fs.
The number of sequential circuit elements included inside an LSI is extremely increased with the integration of LSIs increased. When setting and reading are repetitively carried out for each test pattern in all sequential circuit elements forming scan paths in the above DSPT, not only the test time increases but also a problem occurs that the memory capacity of the tester lacks due to an increase in quantity of the test data. Accordingly, execution of the test in DSPT becomes difficult. Particularly, shortage of the memory capacity of the tester caused by an increase in quantity of test data largely raises the test cost because the memory has to be increased or the tester has to be upgraded.
To solve the above problem, the recent trend is built-in self test (hereinafter referred as BIST). In BIST, patterns generated by a pseudo-random pattern generator 2 are applied to an internal circuit (scan paths) of an LSI, and output results from the internal circuit are verified and stored by an output verifier 7, as shown in FIG. 7. As the pseudo-random pattern generator 2 and the output verifier 7, there are often used linear feedback shift registers (hereinafter referred as LFSRs). Particularly, the output verifier 7 is called a multi-input signature register (hereinafter referred as MISR) since it compresses and stores output results as signatures. Incidentally, FIG. 7 is a diagram for illustrating a known BIST circuit FIG. 7 also shows eight scan paths between the pseudo-random pattern generator 2 and the output verifier 7. Each of the scan paths is formed by serially connecting four F/Fs.
The BIST circuit can generate a large number of test patterns within a short time because the pseudo-random pattern generator is mounted inside the LSI, thus there is no need to store input test patterns in an external tester. Results of the test are compressed and stored by the MISR, so that it is possible to greatly decrease the quantity of data to be loaded to the tester. Further, the BIST circuit can increase the speed of the shifting-in/shifting-out operation to the scan paths by increasing the number of the scan paths, thereby shortening the test time.
Although the above problem with the DSPT can be improved by employing BIST as above, there are still some problems.
Namely, a problem with BIST is the quality of the test (fault coverage) because a pseudo-random pattern is used therein. To increase the fault coverage, it is necessary to apply DSPT as an additional test, or insert a test point, which can improve the controllability and observability, into the circuit inside the LSI.
In BIST, output data are compressed and stored in an MISR. When the MISR captures an indeterminate value (X value) even once, all registers in the MISR become the indeterminate state because of its structure, and values held in the registers are destroyed, which renders the test impossible.
Generally, sequential circuit elements including a RAM inside an LST are in the indeterminate state when the power supply is turned on. For this, it is necessary to beforehand apply a pattern to initialize these sequential circuit elements or take some measures in the circuit to prevent propagation of the indeterminate state to the MISR. Additionally, it is necessary to prevent occurrence of conflict or the floating state of the bus caused by a random pattern when the bus is designed, for example. These severe constraints in design are placed on the designer when the BIST is applied to a practical circuit. Further, there is another problem that area overhead of the circuit or performance degradation occurs because of an additional circuit for BIST and insertion of a test point.
Inventors of this application have proposed a technique disclosed in Japanese Patent Application No. 2000-372231, which can solve the above problems with DSPT and BIST, shorten the test time, decrease the data quantity, and accomplish a high-quality test (test having a high fault coverage). FIG. 8 (block diagram) shows a structure of a test circuit applied this technique.
A test circuit shown in FIG. 8 is based on a BIST circuit similar to that shown in FIG. 7 on an LSI, and a pattern modifier 4 and a mask 5 are added to the BIST circuit. Patterns generated by the pseudo-random pattern generator (LFSR) 2 are modified into patterns equivalent to ones generated by the ATPG, and shifted into the scan paths. After a test clock is applied, outputs from the scan paths are compressed by and stored in the MISR in the output verifier 7 through the mask 5. At this time, an indeterminate value (X value) in the outputs is masked by the mask 5. Incidentally, eight scan paths are shown between the pattern modifier 4 and the mask 5, and each of the scan paths is formed by serially connecting four F/Fs in FIG. 8.
When patterns generated by an ATPG are shifted into scan paths and a test is made, the number of F/Fs to which values (1 or 0) explicitly set on the basis of the patterns is extremely small (several percent) among all F/Fs. In the test circuit shown in FIG. 8, only values to be explicitly set to F/Fs as above are given to the pattern modifier 4 using a control signal from an external tester, and pseudo-random patterns from the pseudo-random pattern generator 2 are modified by the pattern modifier 4 into high-quality patterns equivalent to ones generated by the ATPG. An interminate value is prevented from being captured into the MISR by the mask 5, whereby the designer can do designing in a way to readily and certainly satisfy one of design constrains in BIST, which can largely reduce the burden on the designer.
The LSI testing method of compressing output results and storing them in the MISR as is made in the BIST circuit shown in FIG. 7 or the test circuit shown in FIG. 8 is aimed mainly to judge the quality of an LSI under test. In practical LSI manufacturing, it sometimes becomes necessary to examine a cause of a failure in an LSI that has been judged to have the failure in order to solve a problem in the LSI manufacturing process or improve the yield rate. In such case, it is necessary to specify where the defect exists inside the LSI.
Generally, specifying a position of a fault on the basis of a test pattern given by a tester and information on a portion where an observed value of the tester disagrees with an expected value is called fault diagnosis. Since it is possible to observe outputs of each pattern in DSPT, the fault diagnosis is relatively easy. A fault that can be detected by each pattern and a position (F/F) at which the fault is detected can be known in fault simulation, so that a candidate fault can be narrowed down on the basis of the disagreement information of the tester.
On the contrary, the BIST circuit shown in FIG. 7 or the test circuit shown in FIG. 8 compresses output results and stores them in the MISR of the output verifier 7, and reads out values in the MISR after the test is completed, so that the fault diagnosis is difficult. Namely, even if presence of a fault can be detected, it is impossible to specify a position of the fault because the output results are compressed. Additionally, the number of scan paths is increased to increase the speed of the test in the test such as BIST or the like, so that outputs of all scan paths cannot be observed at external pins because of limitation of the number of pins of an LSI. In other words, the fault diagnosis is impossible.